1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to programmable memory test interfacing logic circuitry and methods for making the same.
2. Description of the Related Art
As semiconductor integrated circuits have become smaller and more densely integrated over the years, there has been increased demands for more comprehensive testing to verify electrical interconnections as well as the integrated circuit's functionality. One type of integrated circuit testing concerns testing the functional characteristics and electrical interconnections of memory devices that may be embedded in, for example, application specific integrated circuits (ASICs). In some applications, as many as 100 random access memories (RAMs) may be embedded in the core logic of a single ASIC, and each memory is typically tested to ensure proper functionality. Because of the dense integration, designers have, for some time, implemented testing circuitry that is embedded directly on the ASIC device to enable rapid verification of the integrity of the millions of electrical interconnections and the functionality of memory devices themselves.
There are a number of well known and commonly used testing methodologies that may be embedded into the ASIC, each requiring special logic circuitry and interfacing connections. The special logic circuitry is typically available in the form of "test collars," which contain the necessary interconnections for performing a desired testing methodology. Because circuit design companies tend to have varying preferences on the types of test collars used in their ASIC applications, each test collar is typically optimized for performing a single type of test methodology. As is well known in the art, typical test methodologies may include a serial built-in-self-test (BIST), a parallel BIST, a parallel test (MUX isolation), a serial memory test and a scan test. For more information on memory testing methodologies, reference may be made to (1) A. L. Silburt, A 180-MHz 0.8 .mu.-m BiCMOS Modular Memory Family of DRAM and Multiport SRAM, IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, March 1993; (2) B. Nadeau-Dostie, Serial Interfacing for Embedded-Memory Testing, IEEE Design and Test of Computers, April 1990; and (3) S. Kornachuk, A High Speed Embedded Cache Design with Non-Intrusive BIST, IEEE International Workshop on Memory Technology Design and Testing, pages 40-45, August 1994. All three articles are incorporated herein by reference.
FIG. 1A shows an application specific integrated circuit (ASIC) 100 having a core logic 102 and a number of embedded test collars for testing memory devices. In this example, ASIC 100 includes a memory core A 104 and a memory core B 106, each having a test collar 110 and a test collar 114, respectively. As described above, test collar 110 and 114 are typically selected by the designer to accomplish a specific memory testing methodology. Once the test collar for performing the designer's chosen testing methodology has been integrated in ASIC 100, a test controller 120 that is specifically chosen to interact with test collars 110 and 114 is also integrated into the ASIC 100.
In addition to embedding test collars 110 and 114 for performing the type of testing methodologies described above, designers also typically integrate scan test collars 108 for testing wire routing and chip logic preceding memory inputs and following memory outputs. As shown, scan collars 108 directly interface with memory core A 104 and memory core B 106, and miscellaneous storage elements 118 (e.g., latches, flip flops, and other memories). As is well known, memory core A 104, memory core B 106, and miscellaneous storage elements 118 are typically interspersed and interconnected with static logic circuitry used when ASIC 100 operates in its mission mode (i.e., non-test mode).
When a scan test is performed, "scan-in" (SI) and "scan-out" (SO) pins located on each scan collar 108 as well as on each storage element contained in miscellaneous storage elements 118, are serially chained together to form one long scan chain. By way of example, FIG. 1B shows a magnification of scan collars 108 and miscellaneous storage elements 118, each having SI and SO pins serially chained together, beginning at a SI pad 122 and ending at a SO pad 124. In this manner, all of the wire routing and chip logic preceding memory inputs and following memory outputs may be conveniently tested directly from the ASIC's bonding pads (e.g., by inputting test vectors into SI pad 122 and checking the results exiting SO pad 124).
Although special test collars for performing serial BIST, parallel BIST, parallel test, and serial test are readily available for integration into most ASIC designs, these test collars typically demand a fair amount of core logic 102 area to be properly laid out. As a result, the necessity to integrating test collars into a multi-memory ASICs has the unfortunate effect of increasing chip size and, therefore packaging sizes.
Yet another drawback of implementing different test collars for performing different types of testing methodologies is, that a substantial amount of design labor and verification goes into integrating test collars into a particular ASIC. For example, assume that design company A prefers to test its ASIC memory devices with a serial BIST methodology and a scan test, and design company B prefers to test its ASIC memory devices with a parallel test and a scan test. Although both design company A and B may be using the same types of memories, such as, for example, a DRAM memory, an SRAM memory or an SDRAM memory, both companies are generally required to perform custom test collar integration to implement their chosen testing methodologies. Although custom test collar integration is typically not a difficult design task, custom integration is generally a time consuming task that may slow down product development and subsequent product release.
In view of the foregoing, there is a need for a memory test interface that may be programmed to perform user selected memory testing methodologies without the need for methodology specific test collars. Further, there is a need for a method of making a memory test interface that may be integrated to a memory device itself, and programmable by a user to perform its preferred memory testing methodology.